Estimation of Analog Parametric Test Metrics Using Copulas

© 2011 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.International audienceA new technique for the estimation of analog parametric test metrics at the design stage is presented in this paper. This technique employs the copulas theory to estimate the distribution between random variables that represent the performances and the test measurements of the circuit under test (CUT). A copulas-based model separates the dependencies between these random variables from their marginal distributions, providing a complete and scale-free description of dependence that is more suitable to be modeled using well-known multivariate parametric laws. The model can be readily used for the generation of an arbitrarily large sample of CUT instances. This sample is thereafter used for estimating parametric test metrics such as defect level (or test escapes) and yield loss. We demonstrate the usefulness of the proposed technique to evaluate a built-in-test technique for a radio frequency low noise amplifier and to set test limits that result in a desired tradeoff between test metrics. In addition, we compare the proposed technique with previous ones that rely on direct density estimation

An analog checker with inputrelative tolerance for duplicate signals

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Enrichment of limited training sets in machine-learning-based analog/RF Test

Abstract-This paper discusses the generation of informationrich, arbitrarily-large synthetic data sets which can be used to (a) efficiently learn tests that correlate a set of low-cost measurements to a set of device performances and (b) grade such tests with parts per million (PPM) accuracy. This is achieved by sampling a non-parametric estimate of the joint probability density function of measurements and performances. Our case study is an ultra-high frequency receiver front-end and the focus of the paper is to learn the mapping between a lowcost test measurement pattern and a single pass/fail test decision which reflects compliance to all performances. The small fraction of devices for which such a test decision is prone to error are identified and retested through standard specification-based test. The mapping can be set to explore thoroughly the tradeoff between test escapes, yield loss, and percentage of retested devices

SymBIST: Symmetry-based Analog/Mixed-Signal BIST

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Symmetry-based A/M-S BIST (SymBIST): Demonstration on a SAR ADC IP

International audienceIn this paper, we propose a defect-oriented Built-In Self-Test (BIST) paradigm for analog and mixed-signal (A/M-S) Integrated Circuits (ICs), called symmetry-based BIST (Sym-BIST). SymBIST exploits inherent symmetries into the design to generate invariances that should hold true only in defect-free operation. Violation of any of these invariances points to defect detection. We demonstrate SymBIST on a 65nm 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) IP by ST Microelectronics

Self-Testing Analog Spiking Neuron Circuit

International audienceHardware-implemented neural networks are foreseen to play an increasing role in numerous applications. In this paper, we address the problem of post-manufacturing test and self-test of hardware-implemented neural networks. In particular, we propose a self-testable version of a spiking neuron circuit. The self-test wrapper is a compact circuit composed of a low-precision ramp generator and a small digital block. The self-test principle is demonstrated on a spiking neuron circuit design in 0.35µm CMOS technology

Compact Functional Testing for Neuromorphic Computing Circuits

We address the problem of testing artificial intelligence (AI) hardware accelerators implementing spiking neural networks (SNNs). We define a metric to quickly rank available samples for training and testing based on their fault detection capability. The metric measures the interclass spike count difference of a sample for the fault-free design. In particular, each sample is assigned a score equal to the spike count difference between the first two top classes. The hypothesis is that samples with small scores achieve high fault coverage because they are prone to misclassification, i.e., a small perturbation in the network due to a fault will result in these samples being misclassified with high probability. We show that the proposed metric correlates with the per-sample fault coverage and that retaining a set of high-ranked samples in the order of ten achieves near-perfect fault coverage for critical faults that affect the SNN accuracy. The proposed test generation approach is demonstrated on two SNNs modeled in Python and on actual neuromorphic hardware. We discuss fault modeling and perform an analysis to reduce the fault space so as to speed up test generation time. © 1982-2012 IEEE

Securing Programmable Analog ICs Against Piracy

International audienceIn this paper, we demonstrate a security approach for the class of highly-programmable analog Integrated Circuits (ICs) that can be used as a countermeasure for unauthorized chip use and piracy. The approach relies on functionality locking, i.e. a lock mechanism is introduced into the design such that unless the correct key is provided the functionality breaks. We show that for highly-programmable analog ICs the programmable fabric can naturally be used as the lock mechanism. We demonstrate the approach on a multi-standard RF receiver with configuration settings of 64-bit words

Techniques de test pour les circuits et systèmes analogiques

The role of nano-electronic systems is rapidly expanding in every facet of modern life. Testing the analog, mixed-signal, and RF (AMS/RF) functions of such systems is considered one of the major bottlenecks and is an area of focus and innovation. Testing is required both in post-manufacturing to guarantee outgoing quality while not sacrificing yield and during the lifetime of operation to detect early reliability hazards and obtain feedback so as to apply corrective actions and continue uninterrupted operation. This talk will cover (a) applications of machine learning and data mining in testing aiming at implicitly predicting AMS/RF performances from low-cost measurements with high confidence; (b) integrated design-for-test and built-in self-test techniques for AMS/RF circuits aiming at reducing the cost of test, facilitating self-calibration and self-healing, and performing on-line test towards achieving fault tolerance; (c) probabilistic test metrics estimation (e.g. defect coverage and yield loss) aiming at evaluating alternative low-cost test solutions during the test development phase before moving to high-volume production; and (d) fault diagnosis for AMS/RF functions aiming at identifying the source of system failure down to transistor level and, thereby, providing feedback for yield enhancement and for avoiding failure reoccurrence. The concepts and methodologies will be demonstrated on industry data sets and on measurements from fabricated circuits.Les prévisions du debut des années 1970 sur le fait que le traitement analogique serait sur le declinen raison de l'avènement des ordinateurs numériques ne se sont jamais concrétisées. En fait, lesavantages de l'informatique numérique sont devenus un facteur important pour l'omniprésence descircuits analogiques. Les principales raisons sont (a) le rôle important des capteurs et des ac-tionneurs dans les systèmes modernes et la nécessité de créer leur interface avec le processeur designaux numériques; (b) le rôle important des communications sans fil où les circuits analogiquesforment l'interface de l'émetteur-récepteur avec l'extérieur; et (c) la nécessité d'améliorer la perfor-mance numérique, par exemple, la nécessite de remodeler par des moyens analogiques les impulsionsnumériques à haute vitesse qui sont déformées.De nos jours, la tendance est à l'intégration des circuits analogiques avec des circuits numériquessur le m^eme substrat de silicium. Lorsque cela est possible, il y a des avantages significatifs: lefacteur de forme du système et la consommation de puissance sont réduits pendant que la vitessede fonctionnement est augmentée. L'intégration à très grande échelle des circuits intégrés mixtesanalogique-numérique est désormais courante dans presque tous les domaines d'applications quiutilisent des puces électroniques. Ces applications comprennent les télécommunications, l'électroniquegrand public, les ordinateurs, le multimédia, l'automobile, l'avionique, l'instrumentation biomédicale,la robotique, etc